1. Field of the Invention
The present invention relates to a pseudo-random noise (PN) series generator used in a digital radio communication technique, and more particularly to a PN series generator capable of changing the timing of generation of a PN series (or the phase of a generated PN series) arbitrarily and with no instantaneous cut-off of the output.
2. Description of the Related Art
The construction of the conventional PN series generator is shown in FIG. 4. A main component of the PN series generator is a tapped shift register (a shift register having taps) 401 whose internal construction is shown in FIG. 5. The register values of the shift register 501 at predetermined positions are added by a mod-2 adder 502 and the result of addition is fed back to the inlet of the shift register 501. When this system is operated by system clocks having a fixed rate, a PN series having a certain period and taking two values of "1" and "0" appears on an output terminal 503. This output is used as an output 402 of the PN series generator as it is.
When this PN series generator is used in a receiver of a radio communication system, there is indispensable a function of changing the timing of generation of a PN series so that it coincides with a received signal. In the case where where it is desired to advance the timing of generation of a PN series by one step, an advance or lead command signal 403 is applied one time from the exterior to operate the tapped shift register 501 at doubled-rate clocks by only one time. On the other hand, in the case where where it is desired to delay the timing of generation of a PN series by one step, a delay or lag command signal 404 is applied one time to stop the operation of the tapped shift register 501 by only one time.
However, the construction of the conventional PN series generator has a problem that it is only one step by one step which the timing of generation of a PN series output can be changed using the advance command signal 403 or the delay command signal 404.
In order to change the timing of generation of a PN series output by two or more steps, it is required that the advance command signal 403 or the delay command signal 404 should be applied plural times. Moreover, the change of the timing is not instantaneous or needs a time until the application of the advance command signal 403 or the delay command signal 404 by required times is completed. During that time, the PN series output cannot be used since a desired timing is not attained.
On the other hand, JP-A-7-86982 has disclosed a synchronous PN code series generating circuit in which the synchronization of a spread PN code series can be established simply between a plurality of communication channels in the case where the PN code series has a very long period. According to the JP-A-7-86982, a feedback shift register circuit common to the plurality of communication channels is provided to generate a PN code series and a shift register circuit of each communication channel generates a spread PN code series for that channel by multiplying the PN code series output from the feedback shift register circuit by mask information which is stored in a mask storage of that channel. However, this synchronous PN code series generating circuit aimed at the synchronization of a spread PN code series for each communication channel is irrelevant to the change of the timing of generation of one PN code series based on a control signal. Further, this synchronous PN code series generating circuit has a very complicated construction since it needs the feedback shift register circuit common to the plurality of communication channels as well as the shift register circuit and the mask storage for each communication channel.
Also, JP-A-7-86984 has disclosed a PN code generator in which PN codes in a spread spectrum communication system can be changed arbitrarily during communication. According to the JP-A-7-86984, a plurality of kinds of PN codes are set and written in a flash memory beforehand and a PN code changed on the basis of a send-and-receive agreement is read from the flash memory at the time of start of communication or at the time of communication. However, this PN code generator has a problem that a flash memory having a large storage capacity is required in order to store a plurality of kinds of PN codes.
Further, JP-A-7-99465 has disclosed an inverse spread code generating circuit in which the efficiency of synchronization capture of inverse spread codes is improved. According to the JP-A-7-99465, inverse spread codes stored in a ROM are read using an address which is incremented or decremented by an up counter or down counter. Therefore, this inverse spread code generating circuit is the same as the PN series generator explained in conjunction with FIG. 4 in that it is only one step by one step which the timing of generation of inverse spread codes can be changed.